ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 43

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
high-side or the low-side output. In addition, the Output
Control Unit allows individual enabling/disabling of each of the
six PWM output signals.
• The Gate Drive Unit permits the generation of the high
frequency chopping frequency and its subsequent mixing with
the PWM signals.
• The PWM Shutdown Controller takes care of the PWM
shutdown via the PWMTRIP pin and generates the correct
RESET signal for the Timing Unit.
Three-phase timing unit
PWM Switching Frequency, PWMDAT0 MMR
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit of
the PWM controller is t
frequency of the MicroConverter. Therefore, for a 45 MHz
f
written to the PWMDAT0 register is effectively the number of
t
PWMDAT0 value is a function of the desired PWM switching
frequency (f
Therefore, the PWM switching period, Ts, can be written as:
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0xFFFF = 65535 which corresponds to a minimum
PWM switching frequency of:
Note that PWMDAT0 value of 0 and 1 are not defined and
CORE
CORE
, the fundamental time increment is 21 ns. The value
clock increments in half a PWM period. The required
f
PWM(min)
PWM
) and is given by:
PWMDAT0 = f
Ts = 2 x PWMDAT0 x t
= 45 x 10
CORE
to interrupt
controller
6
/ (2 x 65535) = 343.99 Hz
= 1/f
core
CORE
/ (2 x f
core clock
where f
CORE
PWM
Configuration
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
Registers
)
CORE
Three-Phase
PWM Timing
Figure 21: Overview of the PWM controller
is the core
Unit
Duty Cycle
Registers
PWMCH0
PWMCH1
PWMCH2
Rev. PrB | Page 43 of 80
Sync
Control
PWMEN
Output
Unit
The PWM sync pulse control unit generates the internal
synchronisation pulse and also controls whether the external
SYNC pin is used or not.
The PWM controller is driven by the ADuC702x core clock
frequency and is capable of generating two interrupts to the
ARM core. One interrupt is generated on the occurrence of a
PWMSYNC pulse and the other is generated on the occurrence
of any PWM shutdown action.
should not be used.
PWM Switching Dead Time, PWMDAT1 MMR
The second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. This is a short delay time introduced between turning off
one PWM signal (e.g. AH) and turning on the complementary
signal (AL). This short time delay is introduced to permit the
power switch being turned off (in this case, AH) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write
PWMDAT1 register. There is only one dead-time register that
controls the dead time inserted into all three pairs of PWM
output signals. The dead time, TD, is related to the value in the
PWMDAT1 register by:
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces an
426 ns delay between the turn-off on any PWM signal (say, AH)
and the turn-on of its complementary signal (AL). The amount
PWMCFG
Drive
Gate
Unit
TD = PWMDAT1 × 2 × t
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
PWMSYNC
PWMTRIP
ADuC702x Series
CORE