ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 44

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
of the dead time can therefore be programmed in increments of
2t
register is a 10-bit register so that its maximum value is 0x3FF
(= 1023), corresponding to a maximum programmed dead time
of:
for a core clock of 45 MHz. Obviously, the dead time can be
programmed to be zero by writing 0 to the PWMDAT1 register.
PWM Operating Mode, PWMCON and PWMSTA MMRs
The PWM controller of the ADuC702x can operate in two
distinct modes, single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 2 of the PWMCON register. If this bit is cleared
the PWM operates in the single update mode. Setting Bit 2
places the PWM in the double update mode. The default
operating mode is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the
PWMDAT1) and the PWM duty cycle registers (PWMCH0,
PWMCH1 and PWMCH2) into the three-phase timing unit. In
addition, the PWMEN register is also latched into the output
control unit on the rising edge of the PWMSYNC pulse. In
effect, this means that the characteristics and resultant duty
cycles of the PWM signals can be updated only once per PWM
period at the start of each cycle. The result is that PWM
patterns that are symmetrical about the midpoint of the
switching period are produced.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers and the PWMEN register. As a result it is possible to
alter both the characteristics (switching frequency and dead
time) as well as the output duty cycles at the midpoint of each
PWM cycle. Consequently, it is possible to produce PWM
switching patterns that are no longer symmetrical about the
midpoint of the period (asymmetrical PWM patterns). In
double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 0 of the PWMSTA register, which is cleared during
operation in the first half of each PWM period (between the
rising edge of the original PWMSYNC pulse and the rising edge
of the new PWMSYNC pulse introduced in double update
mode). Bit 0 of the PWMSTA register is set during operation in
the second half of each PWM period. This status bit allows the
user to make a determination of the particular half-cycle during
implementation of the PWMSYNC interrupt service routine, if
required.
CORE
TD
PWM
(max)
(or 42 ns for a 45 MHz core clock). The PWMDAT1
= 1023 × 2 × t
configuration
CORE
= 1023 × 2 × 22 ×10
registers
(PWMDAT0
–9
= 45.37 µs
Rev. PrB | Page 44 of 80
and
The advantage of double update mode is that lower harmonic
voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Since new duty cycle values
must be computed in each PWMSYNC interrupt service
routine, there is a larger computational burden on the ARM
core in double update mode.
PWM Duty Cycles, PWMCH0, PWMCH1, PWMCH2
MMRs
The duty cycles of the six PWM output signals on pins AH to
CL are controlled by the three 16-bit read/write duty cycle
registers, PWMCH0, PWMCH1 and PWMCH2. The duty cycle
registers are programmed in integer counts of the fundamental
time unit, t
PWM signal produced by the three-phase timing unit over half
the PWM period. The switching signals produced by the three-
phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDAT1 register. The
three-phase timing unit produces active low signals so that a
low level corresponds to a command to turn on the associated
power device.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 22 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time by simply multiplying by the fundamental time increment,
t
symmetrical about the midpoint of the switching period in this
single update mode since the same values of PWMCH0,
PWMDAT0 and PWMDAT1 are used to define the signals in
both half cycles of the period. It can be seen how the
programmed duty cycles are adjusted to incorporate the desired
dead time into the resultant pair of PWM signals. Clearly, the
dead time is incorporated by moving the switching instants of
both PWM signals (0H and 0L) away from the instant set by the
PWMCH0 register. Both switching edges are moved by an
equal amount (PWMDAT1 x
PWMSTA (0)
Figure 22: Typical PWM outputs of Three-Phase timing unit in single update
CORE
PWMSYNC
. First, it is noted that the switching patterns are perfectly
0H
0L
CORE
2 x
PWMDAT1
, and define the desired on-time of the high-side
Preliminary Technical Data
PWMDAT0
PWMCH0
mode
PWMCH0
t
CORE
PWMDAT0
) to preserve the
PWMDAT2+1
PWMDAT1
2 x