ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 52

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
SERIAL PORT MUX
The Serial Port Mux multiplexes the serial port peripherals (two
I
set of ten GPIO pins. Each pin must be configured to one of its
specific I/O function as described in Table 34.
Table 34 details the mode for each of the SPMUX GPIO pins.
This configuration has to be done via the GP0CON, GP1CON
and GP2CON MMRs. By default these ten pins are configured
as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex Universal Asynchronous
Receiver/Transmitter, fully compatible with the 16450 serial
port standard. The UART performs serial-to-parallel conversion
on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters
received from the CPU. The UART includes a fractional divider
for baudrate generation and has a network addressable mode.
The UART function is made available on the following 10 pins
of the ADuC702x:
Pin
SPM0 (mode 1)
SPM1 (mode 1)
SPM2 (mode 1)
SPM3 (mode 1)
SPM4 (mode 1)
SPM5 (mode 1)
SPM6 (mode 1)
SPM7 (mode 1)
SPM8 (mode 2)
SPM9 (mode 2)
The serial communication adopts a asynchronous protocol that
2
C, SPI, UART) and the Programmable Logic Array (PLA) to a
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
GPIO
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
00
Table 35: UART signal description
Table 34: SPM configuration
Signal
RTS
CTS
SIN
SOUT
RI
DCD
DSR
DTR
SIN
SOUT
CONV
UART
SOUT
ECLK
DCD
DTR
CTS
DSR
RTS
SIN
01
RI
Description
Request To Send
Clear To Send
Serial Receive Data
Serial Transmit Data
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
UART/I
I2C0SDA
I2C1SDA
SPIMISO
SPIMOSI
I2C0SCL
I2C1SCL
SPICLK
SPICSL
SOUT
SIN
10
2
C/SPI
PLAO[0]
PLAO[4]
PLAO[5]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLA
11
Rev. PrB | Page 52 of 80
supports various word length, stop bits and parity generation
options selectable in the configuration register.
Baud rate generation
There is two way of generating the UART baudrate.
- Normal 450 UART baudrate generation:
The baudrate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
The following table gives some common baudrate values:
- Using the fractional divider:
The fractional divider combined with the normal baudrate
generator allows the generating of a wider range of more
accurate baudrates.
Calculation of the baudrate using fractional divider is as follow:
Example:
Generation of 9600 baud with CD bits = 3. The previous table
gives DL = 12h.
Core Clock
Baudrate
9600
19200
115200
9600
19200
115200
Baudrate
M
Table 36: baudrate using the normal baudrate generator
+
2048
/(M+N/2048)
Baudrate
N
CD
Figure 26: baudrate generation options
0
0
0
3
3
3
/2
=
Preliminary Technical Data
=
2
CD
Baudrate
×
=
0Ch
92h
49h
12h
DL
9h
1h
16
2
CD
FBEN
×
45
45
45
DL
×
×
.
.
16
.
088
088
088
2
×
CD
baudrate
×
117417
2
Actual
/16DL
19301
19569
88062
MHz
MHz
9651
9785
MHz
2
×
×
×
16
(
M
DL
×
+
DL
2048
UART
N
% error
23.55%
×
0.53%
0.53%
1.92%
1.92%
1.92%
2
)