ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 42

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
DIGITAL PERIPHERALS
THREE-PHASE PWM
General overview
The ADuC702x provides a flexible, programmable, three-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a three-phase voltage
source inverter for ac induction (ACIM) motor control.
The PWM generator produces three pairs of PWM signal on
the six PWM output pins (PWM0H, PWM0L, PWM1H,
PWM1L, PWM2H, and PWM2L). The six PWM output signals
consist of three high-side drive signals and three low-side drive
signals.
The switching frequency and dead time of the generated PWM
patterns are programmable using the PWMDAT0 and
PWMDAT1 MMRs. In addition, three duty-cycle control
registers (PWMCH0, PWMCH1 and PWMCH2) directly
control the duty cycles of the three-pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMEN register. In
addition, three control bits of the PWMEN register permit
crossover of the two signals of a PWM pair. In crossover mode,
the PWM signal destined for the high side switch is diverted to
the complementary low side output and the signal destined for
the low side switch is diverted to the corresponding high side
output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turns on the power devices
of the inverter. In general, there are two common isolation
techniques,
transformer isolation using pulse transformers. The PWM
controller permits mixing of the output PWM signals with a
high frequency chopping signal to permit easy interface to such
pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMCFG register. An 8-bit
value within the PWMCFG register directly controls the
chopping frequency. High frequency chopping can be
independently enabled for the high-side and the low-side
outputs using separate control bits in the PWMCFG register.
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are
symmetrical about the midpoint of the PWM period. In the
double update mode, a second updating of the PWM duty cycle
values is implemented at the midpoint of the PWM period. In
this mode, it is possible to produce asymmetrical PWM
patterns, that produce lower harmonic distortion in three-phase
PWM inverters. This technique also permits closed loop
optical
isolation
using
opto-couplers
Rev. PrB | Page 42 of 80
and
controllers to change the average voltage applied to the machine
windings at a faster rate and so permits faster closed loop
bandwidths to be achieved. The operating mode of the PWM
block is selected by a control bit in the PWMCON register. In
single update mode a PWMSYNC pulse is produced at the start
of each PWM period. In double update mode, an additional
PWMSYNC pulse is produced at the midpoint of each PWM
period.
The PWM block can also provide an internal synchronisation
pulse on the SYNC pin that is synchronise to the PWM
switching frequency. In single update mode a pulse is produce
at the start of each PWM period. In double update mode, an
additional pulse is also produced at the mid-point of each
PWM period. The width of the pulse is programmable through
the PWMDAT2 register. The PWM block can also accept an
external synchronisation pulse on the SYNC pin. The selection
of external synchronisation or internal synchronisation is in the
PWMCON register. The SYNC input timing can be
synchronised to the internal peripheral clock, which is selected
in the PWMCON register. If the external synchronisation pulse
from the chip pin is asynchronous to the internal peripheral
clock (typical case), the external SYNC is considered
asynchronous and should be synchronised. The synchronisation
logic will add latency add jitter from the external pulse to the
actual PWM outputs. The size of the pulse on the SYNC pin
must be greater than two core clock periods.
The PWM signals produced by the ADuC702x can be shut off
via a dedicated asynchronous PWM shutdown pin, PWMTRIP,
that, when brought low, instantaneously places all six PWM
outputs in the OFF state (high). This hardware shutdown
mechanism is asynchronous so that the associated PWM
disable circuitry does not go through any clocked logic, thereby
ensuring correct PWM shutdown even in the event of a loss of
the core clock.
Status information about the PWM system is available to the
user in the PWMSTA register. In particular, the state of the
PWMTRIP pin is available, as well as a status bit that indicates
whether operation is in the first half or the second half of the
PWM period.
Description of the PWM block
A functional block diagram of the PWM controller is shown in
Figure 21. The generation of the six output PWM signals on
pins PWM0H to PWM2L is controlled by four important
blocks:
• The Three-Phase PWM Timing Unit, which is the core of the
PWM controller. It generates three pairs of complemented and
dead-time-adjusted centre-based PWM signals.
• The Output Control Unit allows the redirection of the outputs
of the Three-Phase Timing Unit for each channel to either the
Preliminary Technical Data