ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 46

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
the Output Control Unit so that the signal appears at the 0H
pin. Following a reset, the three crossover bits are cleared so that
the crossover mode is disabled on all three pairs of PWM
signals. The PWMEN register also contains six bits (Bits 0 to 5)
that can be used to individually enable or disable each of the six
PWM outputs. If the associated bit of the PWMEN register is
set, the corresponding PWM output is disabled irrespective of
the value of the corresponding duty cycle register. This PWM
output signal will remain in the OFF state as long as the
corresponding enable/disable bit of the PWMEN register is set.
The implementation of this output enable function is
implemented after the crossover function.
Following a reset, all six enable bits of the PWMEN register are
cleared so that all PWM outputs are enabled by default. In a
manner identical to the duty cycle registers, the PWMEN is
latched on the rising edge of the PWMSYNC signal so that
changes to this register only become effective at the start of each
PWM cycle in single update mode. In double update mode, the
PWMEN register can also be updated at the midpoint of the
PWM cycle.
In the control of an ECM only two inverter legs are switched at
any time and often the high-side device in one leg must be
switched ON at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycles values for
two PWM channels (e.g. PWMCH0 = PWMCH1) and setting
Bit 7 of the PWMEN register to cross over the 1H/1L pair of
PWM signals, it is possible to turn ON the high-side switch of
Phase A and the low-side switch of Phase B at the same time. In
the control of ECM, it is usual for the third inverter leg (Phase
C in this example) to be disabled for a number of PWM cycles.
This function is implemented by disabling both the 2H and 2L
PWM outputs by setting Bits 0 and 1 of the PWMEN register.
This situation is illustrated in Figure 24, where it can be seen
that both the 0H and 1L signals are identical, since PWMCH0 =
PWMCH1 and the crossover bit for phase B is set.
Figure 24. Example active LO PWM signals suitable for ECM control,
0H
0L
1H
1L
2H
2L
2 x PWMDAT1
PWMDAT0
PWMCH0
= PWMCH1
PWMCH0
= PWMCH1
PWMDAT0
2 x PWMDAT1
Rev. PrB | Page 46 of 80
In addition, the other four signals (0L, 1H, 2H and 2L) have
been disabled by setting the appropriate enable/disable bits of
the PWMEN register. For the situation illustrated in Figure 24,
the appropriate value for the PWMEN register is 0x00A7. In
normal ECM operation, each inverter leg is disabled for certain
periods of time so that the PWMEN register is changed based
on the position of the rotor shaft (motor commutation).
Gate Drive Unit
The Gate Drive Unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive
amplifier is used then the active PWM signal must be chopped
at a high frequency. The 10-bit read/write PWMCFG register
allows the programming of this high frequency chopping mode.
The chopped active PWM signals may be required for the high-
side drivers only, for the low-side drivers only or for both the
high-side and low-side switches. Therefore, independent
control of this mode for both high- and low-side switches is
included with two separate control bits in the PWMCFG
register.
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 25. Chopping of the high side PWM outputs (0H, 1H
and 2H) is enabled by setting Bit 8 of the PWMCFG register.
Chopping of the low-side PWM outputs (0L, 1L and 2L) is
enabled by setting Bit 9 of the PWMCFG register. The high
frequency chopping frequency is controlled by the 8-bit word
(GDCLK) placed in Bits 0 to 7 of the PWMCFG register. The
period of this high frequency carrier is:
and the chopping frequency is therefore an integral subdivision
of the MicroConverter core frequency:
The GDCLK value may range from 0 to 255, corresponding to a
programmable chopping frequency rate from 45.9 kHz to 11.75
MHz for a 45 MHz core frequency. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, all bits of the PWMCFG
register are cleared so that high frequency chopping is disabled,
by default.
PWMCH0 = PWMCH1, crossover BH/BL pair and disable 0L, 1H, 2H and 2L
outputs. Operation is in single update mode.
T
f
chop
chop
Preliminary Technical Data
= f
= (4 x (GDCLK + 1)) x t
CORE
/ (4 x (GDCLK + 1))
CORE