ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 62

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC702x integrates a fully Programmable Logic Array
(PLA) which consists of two independent but interconnected
PLA blocks. Each block consists of eight PLA elements, which
gives a total of 16 PLA elements.
A PLA element contains a two-input lookup table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in Figure 27 below.
In total, 30 GPIO pins are available on the ADuC702x for the
PLA. These include 16 input pins and 14 output pins. They need
to be configured in the GPxCON register as PLA pins before
using the PLA. Note that the comparator output is also included
as one of the 16 input pins.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONV
PLA output pins.
The interconnection between the two blocks is supported by
connecting output of element 7 of block 1 fed back to the input
0 of mux 0 of element 0 of block 0, and the output of element 7
Bit
31-11
10-9
8-7
6
5
4-1
START
Description
Reserved
Mux (0) control, select feedback from:
Mux (1) control, select feedback from:
Mux (2) control
Set by user to select the output of mux (1)
Cleared by user to select the bit value from PLADIN
Mux (3) control
Set by user to select the input pin of the particular element
Cleared by user to select the output of mux (0)
Look-up table control
signal of the ADC, to a MMR or to any of the 16
0
1
2
3
Figure 27: PLA element
A
B
LOOK-UP
TABLE
0000 – 0
0001 – NOR
0010 – B AND NOT A
Table 52: PLAELMx MMR Bit Descriptions
4
00 – element 15
01 – element 2
10 – element 4
11 – element 6
00 – element 1
01 – element 3
10 – element 5
11 – element 7
Rev. PrB | Page 62 of 80
PLAELM0
of block 0 is fed back to the input 0 of mux 0 of element 0 of
block 1.
PLA MMRs interface
The PLA peripheral interface consists on 21 MMRs:
- PLAELMx: element0 to element 15 control registers,
- PLACLK: clock selection for the flip-flops of block 0 and
- PLAIRQ: enable IRQ0 or/and IRQ1 and select the source of
- PLAADC: PLA source fro ADC start conversion signal
- PLADIN: data input MMR for PLA
- PLADOUT: data output MMR for PLA. This register is
A PLA tool is provided in the development system to easily
configure the PLA.
configure the input and output mux of each element, select
the function in the lookup table and bypass/use the flip-flop.
clock selection for the flip-flops of block 1
the IRQ
always updated.
Element
0
1
2
3
4
5
6
7
PLAELM1 - 7
element 2
element 4
element 6
element 1
element 3
element 5
element 7
element 0
PLA Block 0
Input
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P0.0
Preliminary Technical Data
Table 51: element input/output
Output
P1.7
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
PLAELM8
element 10
element 12
element 14
element 9
element 11
element 13
element 15
element 7
Element
8
9
10
11
12
13
14
15
PLA Block 1
Input
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PLAELM9-15
element 9
element 8
element 10
element 12
element 14
element 11
element 13
element 15
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7