ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 58

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
7
6
5
4
3
2
1
0
Bit
7-6
5
4
3
2
1
0
Cleared by user, the new serial byte received is discarded
SPITX underflow mode
Set by user to transmit the previous data
Cleared by user to transmit 0
Transfer and interrupt mode (master mode)
Set by user to initiate transfer with a write to the SPITX register. Interrupt will occur when TX is empty
Cleared by user to initiate transfer with a read of the COMRX register. Interrupt will occur when RX is full
LSB first transfer enable bit
Set by user the LSB is transmitted first
Cleared by user the MSB is transmitted first
Reserved
Serial clock polarity mode bit
Set by user, the serial clock idles high
Cleared by user the serial clock idles low
Serial clock phase mode bit
Set by user, the serial clock pulses at the beginning of each serial bit transfer
Cleared by user, the serial clock pulses eat end of each serial bit transfer
Master mode enable bit
Set by user to enable master mode
Cleared by user to enable slave mode
SPI enable bit
Set by user to enable the SPI
Cleared to disable the SPI
Description
Reserved
SPIRX data register overflow status bit
Set if SPIRX is overflowing
Cleared by reading SPISRX register
SPIRX data register IRQ
Set automatically if bit 3 or 5 are set
Cleared by reading SPIRX register
SPIRX data register full status bit
Set automatically if a valid data is present in the SPIRX register
Cleared by reading SPIRX register
SPITX data register underflow status bit
Set automatically if SPITX is under flowing
Cleared by writing in the SPITX register
SPITX data register IRQ
Set automatically if bit 0 is clear or bit 2 is set
Cleared by writing in the SPITX register or if finished transmission disabling the SPI
SPITX data register empty status bit
Set by writing to SPITX to send data. This bit is set during transmission of data
Cleared when SPITX is empty
Table 47: SPISTA MMR Bit Descriptions
Rev. PrB | Page 58 of 80
Preliminary Technical Data