ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 47

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
0H
PWM shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the OFF state, i.e. high state. In addition, the
PWMSYNC pulse is disabled. The PWMTRIP pin has an
internal pull-down resistor so that if the pin becomes
disconnected the PWM will be disabled. The state of the
PWMTRIP pin can be read from Bit 3 of the PWMSTA
register.
On the occurrence of a PWM shutdown command, a
PWMTRIP interrupt will be generated, internal timing of the
three-phase timing unit of the PWM controller is stopped.
Bit
7-5
4
3
2
1
0
Bit
15-10
9
0L
Figure 25: typical PWM signals with high frequency gate chopping enabled
2 x PWMDAT1
Name
PWM_SYNCSEL
PWM_EXTSYNC
PWMDBL
PWM_SYNC_EN
PWMEN
Name
PWMSYNCINT
4 x (GDCLK + 1 ) x t
PWMDAT0
on both high-side and low-side switches
PWMCH0
CORE
Description
Reserved
External sync select
Set to use external sync
Cleared to use internal sync
External sync select
Set to select external synchronous sync signal
Cleared for asynchronous sync signal
Double Update Mode
Set to ‘1’ by the user to enable double update mode
Clear to ‘0’ by the user to enable single update mode
PWM synchronisation enable
Set by user to enable synchronisation
Cleared by user to disable synchronisation
PWM Enable Bit
Set to ‘1’ by the user to enable the PWM
Clear to ‘0’ by the user to disable the PWM. Also cleared automatically with PWMTRIP
Description
Reserved
PWM sync interrupt bit
PWMCH0
PWMDAT0
2 x PWMDAT1
Table 25: PWMCON MMR Bit Descriptions
Table 26: PWMSTA MMR Bit Descriptions
Rev. PrB | Page 47 of 80
Following a PWM shutdown, the PWM can only be re-enabled
(in a PWMTRIP interrupt service routine, for example) by
writing to all of the PWMDAT0, PWMCH0, PWMCH1 and
PWMCH2 registers. Provided the external fault has been
cleared and the PWMTRIP has returned to a high level,
internal timing of the three-phase timing unit resumes and new
duty-cycle values are latched on the next PWMSYNC
boundary.
PWM MMRs interface
The PWM block is controlled via the following nine MMRs:
- PWMCON: control register, enable the PWM, choose the
- PWMSTA: reflects the status of the PWM
- PWMDAT0: unsigned 16-bit register for switching period
- PWMDAT1: unsigned 10-bit register for dead time
- PWMCFG: gate chopping
- PWMCH0,CH1,CH2: channel duty cycle for the three
- PWMEN: allows enabling channel outputs and crossover. See
- PWMDAT2: unsigned 10-bit register for PWM sync pulse
update rate
phases
bit definition Table 28.
width.
ADuC702x Series