AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 196

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.3.3
14.5.3.4
14.5.3.5
14.5.3.6
32099D–06/2010
Enabling the DFLL
Disabling the DFLL
Re-enabling the DFLL
Spread Spectrum Generator (SSG)
Figure 14-4. DFLL Locking in Closed Loop
Before configuring the DFLL, only the EN bit in the DFLL0CONF register should be written to
one. Do not write to any other bits in DFLL0CONF register. The DFLL is now ready for configu-
ration. When PCLKSR.DFLL0RDY is cleared the DFLL clock is ready to be used, if an accurate
clock is required, the clock is not ready to be used before DFLL0LOCKF or DFLL0LOCKA is
asserted.
Writing a zero to DFLL0CONF.EN disables the DFLL. Do not write to any other bits in
D F L L 0 C O N F r e g i s t e r w h e n d i s a b l i n g t h e D F L L . A f t e r d i s a b l i n g t h e D F L L t h e
PCLKSR.DFLL0RDY bit will not be cleared.
After disabling the DFLL the PCLKSR.DFLL0RDY bit will not be cleared. If the DFLL is to be re-
enabled after disabling it, do not wait for PCLKSR.DFLL0RDY to be set to one. Enable the DFLL
by writing the DFLL0CONF.EN bit to one, and do not change any of the other values in the
DFLL0CONF register.
When the DFLL is used as the main clock source for the chip, the EMI radiated from the chip will
be synchronous to the VCO frequency. To provide better EMC capabilities the DFLL can provide
a clock with the energy spread in the frequency domain. This is done by adding or subtracting
values from the FINE value. Enable the SSG by writing a one to the EN bit in the DFLL0SSG
register.
A generic clock sets the rate at which the SSG changes the frequency of the DFLL clock to gen-
erate a spread spectrum (CLK_DFLLIF_DITHER). This is the same clock used by the dithering
mechanism. The frequency of this clock should be higher than CLK_DFLLIF_REF to ensure that
the DFLLIF can lock. Please refer to the Generic clocks section for details.
Optionally, the clock ticks can be qualified by a pseudorandom binary sequence (PRBS) if the
PRBS bit in the DFLL0SSG register is set. This reduces the modulation effect of
CLK_DFLLIF_DITHER frequency onto f
f
f
t
o
f
overshoot
t
coarse
LOCKC
f
coarse
vco
.
t
fine
LOCKF
f
fine
t
accurate
AT32UC3L016/32/64
LOCKA
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