AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 510

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

23.8.2
23.8.2.1
32099D–06/2010
Operation
Bus Timing
TWIS has two modes of operation:
A master is a device which starts and stops a transfer and generates the TWCK clock. A slave
is assigned an address and responds to requests from the master. These modes are
described in the following chapters.
Figure 23-5. Typical Application Block Diagram
The Timing Register (TR) is used to control the timing of bus signals driven by TWIS. TR
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescal-
ing can be selected through TR.EXP.
TR has the following fields:
TLOWS: Prescaled clock cycles used to time SMBUS timeout T
TTOUT: Prescaled clock cycles used to time SMBUS timeout T
SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time T
EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.
f
• Slave transmitter mode
• Slave receiver mode
prescaled
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
=
f
-------------------------- -
2
CLK TWIS
TWD
TWCK
(
EXP
–
Serial EEPROM
+ )
1
Atmel TWI
)
Slave 1
I²C RTC
Slave 2
Controller
I²C LCD
Slave 3
AT32UC3L016/32/64
TIMEOUT
LOW:SEXT
I²C Temp.
Slave 4
Sensor
.
.
Rp
Rp
SU_DAT
VDD
.
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