AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 81

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

9.3
32099D–06/2010
Block Diagram
Figure 9-1
some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB)
and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory
accesses are done via the HSB. The SAU receives an access on its HSB slave interface,
remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its HSB master
interface to the remapped address.
The thin arrows in
read the RX Buffer in the USART. The MPU has been configured to protect all registers in the
USART from user mode access, while the SAU has been configured to remap the RX Buffer
into a memory space that is not protected by the MPU. This unprotected memory space is
mapped into the SAU HSB slave space. When the CPU reads the appropriate address in the
SAU, the SAU will perform an access to the desired RX buffer register in the USART, and
thereafter return the read results to the CPU. The return data flow will follow the opposite
direction of the control flow arrows in
Figure 9-1.
Interrupt
request
Bus slave
presents the SAU integrated in an example system with a CPU, some memories,
Bus master
SAU Block Diagram
SAU Configuration
MPU
CPU
SAU Channel
Figure 9-1
SAU
exemplifies control flow when using the SAU. The CPU wants to
Bus master
Figure
Bus slave
Flash
9-1.
Bus slave
AT32UC3L016/32/64
USART
PWM
High Speed Bus
Bus slave
RAM
Bus bridge
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