AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 412

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

•
Table 20-11.
•
Table 20-12.
•
Table 20-13.
•
32099D–06/2010
CHMODE: Channel Mode
NBSTOP: Number of Stop Bits
PAR: Parity Type
SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
0
0
1
1
0
0
1
1
0
0
0
0
1
1
CHMODE
NBSTOP
If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
If USART operates in SPI Mode (MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
CPOL to produce the required clock/data relationship between master and slave devices.
PAR
0
1
0
1
0
1
0
1
0
0
1
1
0
1
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC = 0)
1 stop bit
1.5 stop bits
2 stop bits
Reserved
0
1
0
1
x
x
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Synchronous (SYNC = 1)
1 stop bit
Reserved
2 stop bits
Reserved
AT32UC3L016/32/64
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