AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 697

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

29.6.2
29.6.3
32099D–06/2010
Configuring the Lookup Table
Output Filter
The lookup table in each LUT unit can generate any logic expression OUT as a function of up to
four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the
LUT.
and the corresponing input and outputs will be IN[4n] to IN[4n+3] and OUTn.
Table 29-2.
By default, the output OUTn is a combinatorial function of the inputs IN[4n] to IN[4n+3]. This may
cause some short glitches to occur when the inputs change value.
It is also possible to clock the output through a filter to remove glitches. This requires that the
corresponding generic clock (GCLK) has been enabled before use. The filter can then be
enabled by writing a one to the Filter Enable (FILTEN) bit in LUTCRn. The OUTn output will be
delayed by three to four GCLK cycles when the filter is enabled.
IN[3]
Table 29-2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Truth Table for the Lookup Table in LUT0
shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn,
IN[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IN[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IN[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AT32UC3L016/32/64
TRUTH0[10]
TRUTH0[11]
TRUTH0[12]
TRUTH0[13]
TRUTH0[14]
TRUTH0[15]
TRUTH0[0]
TRUTH0[1]
TRUTH0[2]
TRUTH0[3]
TRUTH0[4]
TRUTH0[5]
TRUTH0[6]
TRUTH0[7]
TRUTH0[8]
TRUTH0[9]
OUT[0]
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