AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 541

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

24.6.5.2
24.6.6
24.6.7
32099D–06/2010
Open Drain Mode
Synchronization
Interlinked Multiple Value PWM Operation
Figure 24-3. Interlinked Single Value PWM Operation Flow
The interlinked multiple value PWM operation allows up to four channels to be updated simulta-
neously with different duty cycle values. These duty cycle values must be written to the IMDUTY
register. The index number of the four channels to be updated is written to the four SEL fields in
the Interlinked Multiple Value Channel Select (IMCHSEL) register (IMCHSEL.SEL). When the
IMCHSEL register is written, the values stored in the IMDUTY register are synchronized to the
duty cycle registers for the channels selected by the SEL fields.
the writing procedure.
Note that only writes to the implemented channels will be effective. If one of the IMCHSEL.SEL
fields points to a non-existing channel, the corresponding value in the IMDUTY register will not
be written. If the same channel is specified in multiple IMCHSEL.SEL fields, the channel will be
updated with the value stored in the corresponding upper field of the IMDUTY register.
Figure 24-4. Interlinked Multiple Value PWM Operation Flow
Some pins can be used in open drain mode, allowing the PWMA waveform to toggle between
0V and up to 5V on these pins. In this mode the PWMA will drive the pin to zero or leave the out-
put open. An external pullup can be used to pull the pin up to the desired voltage.
To enable open drain mode on a pin the PWMAOD function must be selected instead of the
PWMA function in the I/O Controller. Please refer to the Module Configuration chapter for infor-
mation about which pins are available in open drain mode.
Both the timebase counter and the spread spectrum counter can be reset and the duty cycle
registers can be written through the user interface of the module. This requires a synchroniza-
tion between the PB and GCLK clock domains, which takes a few clock cycles of each clock
domain. The BUSY bit in SR indicates when the synchronization is ongoing. Writing to the mod-
ule while the BUSY bit is set will result in discarding the new value.
DUTYm
ISDUTY
DUTYm
IMDUTY
...
...
DUTY1
DUTY1
ISCHSET
IMCHSEL
MUX
DUTY0
DUTY0
Enable
Write
AT32UC3L016/32/64
Figure 24-4 on page 541
shows
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