AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 658
AT32UC3L064-D3HES
Manufacturer Part Number
AT32UC3L064-D3HES
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3L064-D3HES.pdf
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32099D–06/2010
Figure 28-3. CAT Matrix Connections
In order to use the autonomous QTouch detection capability, the user must first set up the
Autonomous Touch Pin Select Register (ATPINS) and Autonomous Touch Configuration Regis-
ters (ATCFG0 through 3) with appropriate values. The module can then be enabled using the
Control Register (CTRL). After the module is enabled, the module will acquire data from the
autonomous QTouch sensor and use it to determine whether the sensor is activated. The
active/inactive status of the autonomous QTouch sensor is reported in the Status Register (SR),
and it is also possible to configure the CAT to generate an interrupt whenever the status
changes. The module will continue acquiring autonomous QTouch sensor data and updating
autonomous QTouch status until the module is disabled or reset.
In order to use the QMatrix, QTouch group A, or QTouch group B acquisition capabilities, it is
first necessary to set up the appropriate pin mode registers (PINMODE0 and PINMODE1) and
configuration registers (MGCFG0, MGCFG1, TGACFG0, TGACFG1, TGBCFG0, and
TGBCFG1). The module must then be enabled using the CTRL register. In order to initiate
acquisition, it is necessary to perform a write to the Acquisition Initiation and Selection Register
(AISR). The specific value written to AISR determines which type of acquisition will be per-
formed: QMatrix, QTouch group A, or QTouch group B. The CPU can initiate acquisition by
writing to the AISR.
While QMatrix, QTouch group A, or QTouch group B acquisition is in progress, the module col-
lects count values from the sensors and buffers them. Availability of acquired count data is
indicated by the Acquisition Ready (ACREADY) bit in the Status Register (SR). The CPU or the
Peripheral DMA Controller can then read the acquired counts from the ACOUNT register.
32-bit AVR
Chip
ACREFN
VDIVEN
SMP
YK0
YK1
DIS
X2
X3
X6
X7
Y0
Y1
Rdis
Cs1 (Sense Capacitor)
Rsmp1
Cs0 (Sense Capacitor)
Ra
Rb
NOTE: If the CAT internal
current sources will be enabled,
the SMP signal and Rsmp
resistors should NOT be included
in the design. If the CAT internal
current sources will NOT be
enabled, the DIS signal and Rdis
resistor should NOT be included
in the design.
QMatrix Sensor Array
AT32UC3L016/32/64
Rsmp0
658
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