AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 257

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

15.5.5
15.5.6
15.5.7
32099D–06/2010
AST wakeup
Shutdown Mode
Digital Tuner
The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register
is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable
(EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD)
register.
The AST can wake up the CPU directly, without the need to trigger an interrupt. A wakeup can
be generated when the counter overflows, when the counter reaches the selected alarm value,
or when the selected prescaler bit has a 0-to-1 transition. In this case, the CPU will continue
executing from the instruction following the sleep instruction.
The AST wakeup is enabled by writing a one to the corresponding bit in the Wake Enable Regis-
ter (WER). When the CPU wakes from sleep, the wake signal must be cleared by writing a one
to the corresponding bit in SCR to clear the internal wake signal to the sleep controller. If the
wake signal is not cleared after waking from sleep, the next sleep instruction will have noe effect
because the CPU will wake immediately after this sleep instruction.
The AST wakeup can wake the CPU from any sleep mode where the source clock is active. The
AST wakeup can be configured independently of the interrupt masking.
If the AST is configured to use a clock that is available in Shutdown mode, the AST can be used
to wake up the system from shutdown. Both the alarm wakeup, periodic wakeup, and overflow
wakeup mechanisms can be used in this mode.
When waking up from Shutdown mode all control registers will have the same value as before
the shutdown was entered, except the Interrupt Mask Register (IMR). IMR will be reset with all
interrupts turned off. The software must first reconfigure the interrupt controller and then enable
the interrupts in the AST to again receive interrupts from the AST.
The CV register will be updated with the current counter value directly after wakeup from shut-
down. The SR will show the status of the AST, including the status bits set during shutdown
operation.
When waking up the system from shutdown the CPU will start executing code from the reset
start address.
The digital tuner adds the possibility to compensate for a too slow or a too fast input clock. The
ADD bit in the Digital Tuner Register (DTR.ADD) selects if the tuned frequency should be
reduced or increased. The resulting frequency is
for
by writing the selected value to the corresponding filed in DTR. If
unchanged.
VALUE 0
>
, where
f
0
is the original frequency of the prescaler. VALUE and EXP are chosen
f
TUNED
=
f
0





1
±
-------------------------------------------------------------------- -


------------------- -
VALUE
1
AT32UC3L016/32/64


⋅
(
2
1
(
EXP
VALUE
+
8
)
)
–
=
1
0





, the frequency is
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