AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 801

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AT32UC3L064-D3HES

Manufacturer Part Number
AT32UC3L064-D3HES
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
35.2.4
35.2.5
32099D–06/2010
SCIF
AST
4. Instability when exiting sleep walking
5. Clock Failure Detector (CFD) can be issued while turning off the CFD
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
1. Reset may set status bits in the AST
2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface.
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective.
Fix/Workaround
- Do not disable POR33 using the user interface.
- Do not use the SM33 supply monitor.
- Do not enter Shutdown mode if a debugger is connected to the chip.
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
-The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
-A sleep mode where the OSC0 is automatically disabled is entered
-The chip enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleep walking is expected to be used.
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter-
ing sleep mode.
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
AT32UC3L016/32/64
801

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