AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 480

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 22-9. Master Read with Multiple Data Bytes
22.8.5
22.8.5.1
32099D–06/2010
SR.IDLE
RXRDY
TWD
Using the Peripheral DMA Controller
NBYTES set to m
Write START +
Data Transmit with the Peripheral DMA Controller
S
STOP bit
DADR
Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with
no data bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the
master to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the trans-
fer is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 22-8. Master Read with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The program-
mer can set up ring buffers for the DMA controller, containing data to transmit or free buffer
space to place received data.
To assure correct behavior, respect the following programming sequences:
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
R
A
SR.IDLE
RXRDY
TWD
DATAn
NBYTES set to 1
Write START &
S
STOP bit
Read RHR
DADR
DATAn
A
DATAn+1
R
DATAn+m-2
Read RHR
A
DATAn+m-1
DATA
AT32UC3L016/32/64
DATAn+m-1
Read RHR
A
N
Read RHR
DATAn+m
When NBYTES=0
P
Send STOP
N
Read RHR
DATAn+m
P
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