AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 557
AT32UC3L064-D3HES
Manufacturer Part Number
AT32UC3L064-D3HES
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3L064-D3HES.pdf
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24.8
32099D–06/2010
Module Configuration
The specific configuration for each PWMA instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 24-4.
Table 24-5.
Table 24-6.
Feature
Number of PWM channels
Channels supporting incoming peripheral events
PWMA channels with Open Drain mode
Clock Name
CLK_PWMA
GCLK
Register
VERSION
PARAMETER
PWMA Configuration
PWMA Clocks
Register Reset Values
Reset Value
0x00000101
0x00000024
Descripton
Clock for the PWMA bus interface
The generic clock used for the PWMA is GCLK3
AT32UC3L016/32/64
PWMA
36
0, 6, 8, 9, 11, 14, 19, and 20
21, 27, and 28
557
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