OR3T125 Agere Systems, OR3T125 Datasheet - Page 125

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OR3T125

Manufacturer Part Number
OR3T125
Description
3C and 3T Field-Programmable Gate Arrays
Manufacturer
Agere Systems
Datasheet

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Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
50 pF.
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock Q of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at
one of the six ExpressCLK inputs of the device, and that a PIO FF be used.
ECLK Middle Input Pin OUTPUT Pin
ECLK Middle Input Pin OUTPUT Pin
ECLK Middle Input Pin OUTPUT Pin
Additional Delay if ECLK Corner Pin Used
(Fast)
(Slewlim)
(Sinklim)
(T
J
= 85 °C, V
Description
DD
DD
DD
= min)
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
ECLK
(continued)
Figure 76. ExpressCLK to Output Delay
CLKCNTRL
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
<
OR3T125
OR3T125
OR3T125
OR3T125
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
Device
T
ECLK
A
<
<
T
A
70 °C; Industrial: V
D
<
PIO FF
70 °C; Industrial: V
Q
Min
-4
10.10
12.37
12.54
13.73
13.90
Max
9.93
1.97
1.97
OUTPUT (50 pF LOAD)
DD
= 5.0 V ± 10%, –40 °C
DD
Min
= 3.0 V to 3.6 V, –40 °C
ORCA Series 3C and 3T FPGAs
-5
10.07
10.27
11.12
11.18
11.30
11.42
11.62
Max
7.78
7.84
7.96
8.08
8.28
9.77
9.83
9.95
1.91
1.91
1.91
1.91
1.90
Speed
Min
-6
<
10.92
10.95
11.00
11.06
11.16
5.40
5.43
5.48
5.54
5.64
6.07
6.10
6.15
6.21
6.31
1.80
1.90
2.09
2.28
2.57
Max
T
A
<
<
+85 °C; C
T
A
Min
<
+85 °C;C
-7
Max
4.38
4.40
4.44
4.49
4.58
4.91
4.93
4.97
5.02
9.65
9.67
9.71
9.76
9.85
1.58
1.67
1.84
2.02
2.29
5.11
L
= 50 pF.
5-4846(F).a
L =
125
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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