OR3T125 Agere Systems, OR3T125 Datasheet - Page 5

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Contents
Data Sheet
June 1999
Figure 54. Master Parallel Configuration Schematic 92
Figure 55. Master Serial Configuration Schematic ... 93
Figure 56. Asynchronous Peripheral Configuration .. 94
Figure 57. PowerPC /MPI Configuration Schematic .. 95
Figure 58. i960 /MPI Configuration Schematic .......... 95
Figure 59. Configuration Through MPI ..................... 95
Figure 60. Readback Through MPI .......................... 96
Figure 61. Slave Serial Configuration Schematic ..... 97
Figure 62. Slave Parallel Configuration Schematic .. 97
Figure 63. Daisy-Chain Configuration Schematic ..... 98
Figure 64. Combinatorial PFU Timing .................... 105
Figure 65. Synchronous Memory Write
Figure 66. Synchronous Memory Read Cycle ........ 110
Figure 67. MPI PowerPC User Space Read Timing 117
Figure 68. MPI PowerPC User Space Write Timing 117
Figure 69. MPI PowerPC Internal Read Timing ..... 118
Figure 70. MPI PowerPC Internal Write Timing ...... 118
Figure 71. MPI i960 User Space Read Timing ....... 119
Figure 72. MPI i960 User Space Write Timing ....... 119
Figure 73. MPI i960 Internal Read Timing .............. 120
Figure 74. MPI i960 Internal Write Timing .............. 120
Figure 75. Boundary-Scan Timing Diagram ........... 122
Figure 76. ExpressCLK to Output Delay ................ 125
Figure 77. Fast Clock to Output Delay ................... 126
Figure 78. System Clock to Output Delay .............. 127
Figure 79. Input to ExpressCLK Setup/Hold Time .. 129
Figure 80. Input to Fast Clock Setup/Hold Time ..... 131
Figure 81. Input to System Clock Setup/Hold Time 132
Lucent Technologies Inc.
Explicit Mode ........................................................... 90
Characteristics ...................................................... 109
Table of Contents
Page
Contents
Figure 82. General Configuration Mode Timing
Figure 83. Master Serial Configuration Mode
Figure 84. Master Parallel Configuration Mode
Figure 85. Asynchronous Peripheral Configuration
Figure 86. Slave Serial Configuration Mode
Figure 87. Slave Parallel Configuration Mode
Figure 88. Readback Timing Diagram ....................142
Figure 89. ac Test Loads ........................................143
Figure 90. Output Buffer Delays .............................143
Figure 91. Input Buffer Delays ................................143
Figure 92. Sinklim (T
Figure 93. Slewlim (T
Figure 94. Fast (T
Figure 95. Sinklim (T
Figure 96. Slewlim (T
Figure 97. Fast (T
Figure 98. Sinklim (T
Figure 99. Slewlim (T
Figure 100. Fast (T
Figure 101. Sinklim (T
Figure 102. Slewlim (T
Figure 103. Fast (T
Figure 104. Package Parasitics ..............................196
Diagram .................................................................135
Timing Diagram .....................................................136
Timing Diagram .....................................................137
Mode Timing Diagram ...........................................138
Timing Diagram .....................................................139
Timing Diagram .....................................................140
ORCA Series 3C and 3T FPGAs
J
J
J
J
°C, V
= 125 °C, V
J
J
J
= 25 °C, V
= 125 °C, V
J
J
J
J
= 25 °C, V
= 125 °C, V
= 25 °C, V
J
= 25 °C, V
= 125 °C, V
= 25 °C, V
= 125 °C, V
= 125 °C, V
DD
= 5.0 V) ......................144
DD
DD
DD
DD
DD
DD
DD
DD
= 4.5 V) ............144
= 3.3 V) ............145
DD
DD
= 3.0 V) ..........145
DD
= 5.0 V) ..........144
= 3.3 V) ..........145
= 5.0 V) .........144
= 3.3 V) .........145
= 4.5 V) ........144
= 4.5 V) .......144
= 3.0 V) ......145
= 3.0 V) .....145
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