OR3T125 Agere Systems, OR3T125 Datasheet - Page 17

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
Programmable Logic Cells
The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K
any equation created from K
case, they have been set to the propagate and gener-
ate functions.
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition or
subtraction is input on ASWE, with a logic 0 indicating
subtraction and a logic 1 indicating addition. The result
bit is created in one-half of the LUT from a single bit
from each input bus K
bit.
The second submode is the counter submode (see
Figure 7). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input K
be incremented by one for an up counter or decre-
mented by one for a down counter. If an up/down
counter is needed, the control signal to select the direc-
tion (up or down) is input on ASWE with a logic 1 indi-
cating an up counter and a logic 0 indicating a down
counter. Generally, the latches/FFs in the same PFU
are used to hold the present count value.
Lucent Technologies Inc.
Z
[0], and then output F[7:0]/F[3:0] will either
7
/K
3
). Both of these outputs can be
Z
[1:0], along with the ripple input
Z
[1] and K
(continued)
Z
[0], but in this
CIN/FCIN
K
K
K
K
K
K
K
K
7
6
5
4
3
2
1
0
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
Figure 7. Counter Submode
ORCA Series 3C and 3T FPGAs
K
K
K
K
K
K
K
K
7
6
5
4
3
2
1
0
C
C
D
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
REGCOUT
FCOUT
COUT
F7
Q7
F6
Q6
F5
Q5
F4
Q4
F3
Q3
F2
Q2
F1
Q1
F0
Q0
5-5756(F)
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