OR3T125 Agere Systems, OR3T125 Datasheet - Page 36

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
The programmable input/output cells (PICs) are
located along the perimeter of the device. The PIC’s
name is represented by a two-letter designation to indi-
cate on which side of the device it is located followed by
a number to indicate in which row or column it is
located. The first letter, P , designates that the cell is a
PIC and not a PLC. The second letter indicates the side
of the array where the PIC is located. The four sides
are left (L), right (R), top (T), and bottom (B). The indi-
vidual I/O pad is indicated by a single letter (either A, B,
C, or D) placed at the end of the PIC name. As an
example, PL10A indicates a pad located on the left
side of the array in the tenth row.
Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os (PIOs) and significant
routing resources. Each PIO contains input buffers,
output buffers, routing resources, latches/FFs, and
logic and can be configured as an input, output, or
bidirectional I/O.
36
36
OUT1
OUT2
ECLK
SCLK
LSR
CE
ENABLE_GSR
DISABLE_GSR
0
Figure 22 . OR3C/Txxx Programmable Input/Output (PIO) Image from ORCA Foundry
1
0
0
CE_OVER_LSR
LSR_OVER_CE
ASYNC
AND
NAND
OR
NOR
XOR
XNOR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
PIO LOGIC
PMUX
D
CK
SP
LSR
Q
RESET
SET
TS
D0 Q
CK
LSR
1
BUFFER
MODE
FAST
SLEW
SINK
PULL-MODE
LEVEL MODE
PICs in the Series 3 FPGAs have significant local rout-
ing resources, similar to routing in the PLCs. This new
routing increases the ability to fix user pinouts prior to
placement and routing of a design and still maintain
routability. The flexibility provided by the routing also
provides for increased signal speed due to a greater
variety of signal paths possible.
Included in the PIC routing is a fast path from the input
pins to the SLICs in each of the three adjacent PLCs
(one orthogonal and two diagonal). This feature allows
for input signals to be very quickly processed by the
SLIC decoder function and used on-chip or sent back
off of the FPGA. Also new to the Series 3 PIOs are
latches and FFs and options for using fast, dedicated
clocks called ExpressCLKs. These features will all be
discussed in subsequent sections.
A diagram of a single PIO (one of four in a PIC) is
shown in Figure 22. Table 9 provides an overview of the
programmable functions in an I/O cell.
UP
DOWN
NONE
PAD
TTL
CMOS
PD
ECLK
SCLK
1
INREGMODE
NORMAL
INVERTED
LATCHFF
LATCH
FF
Lucent Technologies Inc.
D
CK
Q
RESET
SET
D0
D1
CK
SP
SD
LSR
Q
Data Sheet
June 1999
CLKIN
5-5805(F).c
IN1
IN2