OR3T125 Agere Systems, OR3T125 Datasheet - Page 149

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
Lucent Technologies Inc.
Pin Information
Pin Descriptions
This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration.
Table 67. Pin Descriptions
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
Dedicated Pins
Special-Purpose Pins
RD_DATA/TDO
M0, M1, M2
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
Symbol
RD_CFG
RESET
DONE
CCLK
PRGM
V
GND
V
DD
DD
5
I/O
I/O
—
—
—
O
O
I
I
I
I
I
I
Positive power supply.
Ground supply.
5 V tolerant select. V
OR2TxxA devices. Connections to 5 V power sources are not used for 5 V tolerant
I/Os in the OR3Txxx devices.
During configuration,
enabled. After configuration,
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
In the master and asynchronous peripheral modes, CCLK is an output which
strobes configuration data in. In the slave or synchronous peripheral mode, CCLK
is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK
is used internally and output for daisy-chain operation.
As an input, a low level on DONE delays FPGA start-up after configuration (see
Note).
As an active-high, open-drain output, a high level on this signal indicates that config-
uration is complete. DONE has an optional pull-up resistor.
PRGM
boundary-scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the
This pin always has an active pull-up.
During configuration,
tion and 3-states all of the I/O.
After configuration,
TS_ALL function as described above, or, if readback is enabled via a bit stream
option, a high-to-low transition on
data, including PFU output states, starting with frame address 0.
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-
figuration data out. If used in boundary scan, TDO is test data out.
During powerup and initialization, M0—M2 are used to select the configuration
mode with their values latched on the rising edge of
uration modes. During configuration, a pull-up is enabled.
After configuration, these pins are user-programmable I/O (see Note).
is an active-low input that forces the restart of configuration and resets the
RD_CFG
DD
RESET
RD_CFG
5 pin locations are shown for package compatibility with
can be selected (via a bit stream option) to activate the
forces the restart of configuration and a pull-up is
RESET
is an active-low input that activates the TS_ALL func-
RD_CFG
Description
can be used as a general FPGA input or as a
will initiate readback of the configuration
ORCA Series 3C and 3T FPGAs
INIT
; see Table 34 for the config-
INIT
pin goes high.
149