OR3T125 Agere Systems, OR3T125 Datasheet - Page 131

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Input to FCLK Hold Time (middle
Input to FCLK Hold Time (corner
Input to FCLK Hold Time (corner
ECLK pin, delayed data input)
ECLK pin)
ECLK pin, delayed data input)
(T
J
= 85 °C, V
Description
DD
= min)
DD
DD
= 5 .0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
Figure 80. Input to Fast Clock Setup/Hold Time
(continued)
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3T125
OR3T125
OR3T125
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
Device
INPUT
ECLK
<
T
<
A
T
<
0.00
0.00
8.43
9.09
0.00
0.00
Min
A
—
—
—
—
—
—
—
—
—
70 °C; Industrial: V
<
70 °C; Industrial: V
-4
CLKCNTRL
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FCLK
0.00
0.00
0.00
0.00
0.00
6.26
6.49
6.98
7.53
8.45
0.00
0.00
0.00
0.00
0.00
Min
DD
-5
D
PIO FF
DD
= 5.0 V ± 10%, –40 °C
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= 3.0 V to 3.6 V, –40 °C
Q
Speed
ORCA Series 3C and 3T FPGAs
0.00
0.00
0.00
0.00
0.00
5.54
5.72
6.09
6.47
7.10
0.00
0.00
0.00
0.00
0.00
Min
-6
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
<
T
0.00
0.00
0.00
0.00
0.00
4.88
5.04
5.40
5.79
6.40
0.00
0.00
0.00
0.00
0.00
A
Min
<
<
T
A
+85 °C.
-7
<
+85 °C.
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5-4847(F).a
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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