OR3T125 Agere Systems, OR3T125 Datasheet - Page 136

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 61 . Master Serial Configuration Mode Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
* Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since
the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge.
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.
136
DIN Setup Time*
DIN Hold Time
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
Parameter
DOUT
CCLK
DIN
DD
DD
Figure 83. Master Serial Configuration Mode Timing Diagram
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
S
(continued)
BIT N
<
Symbol
T
T
<
A
T
T
F
F
T
H
H
C
C
D
S
<
T
A
70 °C; Industrial: V
<
70 °C; Industrial: V
T
D
60.00
0.00
5.00
0.63
Min
DD
—
BIT N
DD
= 5.0 V ± 10%, –40 °C
= 3.0 V to 3.6 V, –40 °C
16.67
Max
2.08
5.00
—
—
Lucent Technologies Inc.
<
T
A
<
<
T
+85 °C.
A
<
Data Sheet
June 1999
+85 °C.
MHz
MHz
Unit
ns
ns
ns
5-4532(F)