OR3T125 Agere Systems, OR3T125 Datasheet - Page 98

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
Daisy-Chaining
Multiple FPGAs can be configured by using a daisy-
chain of the FPGAs. Daisy-chaining uses a lead FPGA
and one or more FPGAs configured in slave serial
mode. The lead FPGA can be configured in any mode
except slave parallel mode. (Daisy-chaining is available
with the boundary-scan ram_w instruction discussed
later.)
All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on positive CCLK and out on negative CCLK
edges.
An upstream FPGA that has received the preamble
and length count outputs a high on DOUT until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bit
pairs. After loading and retransmitting the preamble
and length count to a daisy-chain of slave devices, the
lead device loads its configuration data frames.
As seen in Figure 63, the
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
98
98
PROGRAM
EPROM
A[17:0]
D[7:0]
OE
CE
V
DD
GND
V
OR
DD
INIT
DONE
PRGM
CCLK
A[17:0]
D[7:0]
M2
M1
M0
pins for all of the FPGAs are connected together. This is required to guarantee that
Figure 63. Daisy-Chain Configuration Schematic
MASTER
SERIES
ORCA
FPGA
(continued)
DOUT
RCLK
HDC
INIT
LDC
V
DD
CCLK
DIN
DONE
M2
M1
M0
PRGM
The loading of configuration data continues after the
lead device has received its configuration data if its
internal frame bit counter has not reached the length
count. When the configuration RAM is full and the num-
ber of bits received is less than the length count field,
the FPGA shifts any additional data out on DOUT.
The configuration data is read into DIN of slave devices
on the positive edge of CCLK, and shifted out DOUT
on the negative edge of CCLK. Figure 63 shows the
connections for loading multiple FPGAs in a daisy-
chain configuration.
The generation of CCLK for the daisy-chained devices
that are in slave serial mode differs depending on the
configuration mode of the lead device. A master paral-
lel mode device uses its internal timing generator to
produce an internal CCLK at eight times its memory
address rate (RCLK). The asynchronous peripheral
mode device outputs eight CCLKs for each write cycle.
If the lead device is configured in slave mode, CCLK
must be routed to the lead device and to all of the
daisy-chained devices.
SLAVE #1
SERIES
ORCA
FPGA
DOUT
RCLK
HDC
LDC
INIT
V
DD
DIN
DONE
PRGM
M2
M1
M0
CCLK
Lucent Technologies Inc.
SLAVE #2
SERIES
ORCA
FPGA
DOUT
RCLK
Data Sheet
HDC
LDC
June 1999
INIT
V
V
5-4488(F
DD
DD