OR3T125 Agere Systems, OR3T125 Datasheet - Page 80

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
PCM Detailed Programming
Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to
Figure 46 for more information on the location of the PCM elements that are discussed. In the following discussion,
the duty cycle is in the percentage of the clock period where the clock is high.
Table 31
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Register 0—Divider 0 Programming
Register 1—Divider 1 Programming
Register 2—Divider 2 Programming
Register 3—DLL 2x Duty-Cycle Programming
Bits [3:0]
Bits [6:4]
Bits [3:0]
Bits [6:4]
Bits [3:0]
Bits [6:4]
Bits [2:0]
Bits [5:3]
Bit #
Bit 7
Bit 7
Bit 7
Bit 6
Bit 7
.
PCM Control Registers
4-Bit Divider, DIV0, Value. This value enables the input clock to immediately be divided by a
value from 1 to 8. A 0 value (the default) indicates that DIV0 is bypassed (no division). Bypass
incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their
modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder
9/8 = 1).
Reserved.
DIV 0 Reset Bit. DIV0 may not be reset by GSRN depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV0 to its default value. Bit 0 must be set to 0 (the default) to
remove the reset.
4-Bit Divider, DIV1, Value. This value enables the feedback clock to be divided by a value from
1 to 8. A 0 value (the default) indicates that DIV1 is bypassed (no division). Bypass incurs less
delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8
value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1).
Reserved.
DIV1 Reset Bit. DIV1 may not be reset by GSRN, depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV1 to its default value. Bit 0 must be set to 0 (the default) to
remove the reset.
4-Bit Divider, DIV2, Value. This value enables the tapped delay line output clock driven onto
ExpressCLK to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV2 is
bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater
than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the
result is divide by 1 (remainder 9/8 = 1).
Reserved.
DIV2 Reset Bit. DIV2 may not be reset by GSRN, depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV2 to its default value. Bit 7 must be set to 0 (the default) to
remove the reset.
Duty-cycle selection for the doubled clock period associated with the input clock high. The duty
cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6.
Duty-cycle selection for the doubled clock period associated with the input clock low. The duty
cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7.
Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to
50%, 1 = greater than 50%.
to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0]
are 11 001 001.
Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal
(continued)
Function
Lucent Technologies Inc.
Data Sheet
June 1999