OR3T125 Agere Systems, OR3T125 Datasheet - Page 138

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 63 . Asynchronous Peripheral Configuration Mode Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0].
D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by
138
* This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.
WR, CS0, and CS1 Pulse Width
D[7:0] Setup Time:
D[7:0] Hold Time
RDY Delay
RDY Low
Earliest WR After RDY Goes High*
RD to D7 Enable/Disable
CCLK to DOUT
3Cxx
3Txxx
DOUT
CCLK
RDY
CS0
CS1
WR
D7
RD
Parameter
Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
PREVIOUS BYTE
(continued)
Symbol
<
T
T
T
T
WR2
T
T
RDY
DEN
T
T
T
WR
T
<
A
H
D
S
B
S
T
<
WRITE DATA
T
WR
A
70 °C; Industrial: V
<
70 °C; Industrial: V
T
T
D
RDY
T
50.00
20.00
10.50
D7
0.00
1.00
0.00
Min
H
—
—
—
DD
DD
= 5.0 V ± 10%, –40 °C
D0
= 3.0 V to 3.6 V, –40 °C
T
B
T
DEN
D1
T
40.00
40.00
Max
8.00
5.00
WR2
—
—
—
—
—
RD.
D2
Lucent Technologies Inc.
<
T
T
A
DEN
<
<
T
+85 °C.
A
D3
CCLK Periods
<
Data Sheet
June 1999
+85 °C.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
5-4533(F)