OR3T125 Agere Systems, OR3T125 Datasheet - Page 134

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OR3T125

Manufacturer Part Number
OR3T125
Description
3C and 3T Field-Programmable Gate Arrays
Manufacturer
Agere Systems
Datasheet

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ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 60. General Configuration Mode Timing Characteristics (continued)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Note: T
134
Slave Parallel Mode
Power-on Reset Delay
CCLK Period:
Configuration Latency (normal mode):
Partial Reconfiguration (explicit mode):
INIT
INIT
Initialization Latency (
INIT
Slave Parallel
Slave Serial
Master Serial:
Master Parallel:
OR3T125
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
OR3T125
OR3Cxx
OR3Txxx
OR3T20
OR3T30
OR3C55
OR3T55
OR3C80
OR3T80
OR3T125
OR3T20
OR3T30
OR3C55
OR3T55
OR3C80
OR3T80
OR3T20
OR3T30
OR3C/T55
OR3C/T80
Timing
High to CCLK Delay:
High to
PO
is triggered when V
WR
, Asynchronous Peripheral
Parameter
DD
DD
PRGM
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx.
high to
(continued)
INIT
high):
<
T
<
A
<
T
A
70 °C; Industrial: V
<
70 °C; Industrial: V
T
T
Symbol
INIT_CCLK
T
INIT_WR
T
T
T
CCLK
T
PO
PR
CL
IL
DD
DD
= 5.0 V ± 10%, –40 °C
40.00
15.00
3.90
0.36
0.47
1.94
0.72
2.81
1.05
1.64
0.48
0.54
1.72
0.65
2.04
0.77
0.93
1.00
1.00
1.00
0.50
4.80
1.00
0.21
0.24
0.30
0.36
0.45
2.00
= 3.0 V to 3.6 V, –40 °C
Min
13.10
16.20
Lucent Technologies Inc.
3.40
2.00
3.60
0.68
0.79
1.00
1.20
1.50
Max
<
T
A
<
<
T
+85 °C.
A
<
Data Sheet
June 1999
+85 °C.
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
ns
µs
µs
µs
µs
µs
µs
µs

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