S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 1017

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 27
512 KByte Flash Module (S12XFTM512K3V1)
Freescale Semiconductor
Revision
Number
V01.09
V01.10
V01.11
14 Nov 2007
19 Dec 2007
25 Sep 2009
Revision
Date
27.5.2/27-1077
27.4.2/27-1053
27.4.2/27-1053
27.3.2/27-1027
27.1/27-1018
27.4.2.12/27-
27.4.2.12/27-
27.4.2.12/27-
27.4.2.20/27-
27.6/27-1077
27.4.2.8/27-
27.3.2.1/27-
27.4.2.4/27-
27.4.2.7/27-
27.3.2.1/27-
27.4.1.2/27-
Sections
Affected
1059
1029
1056
1058
1062
1062
1062
1071
1029
1048
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 27-1. Revision History
- Changed terminology from ‘word program’ to “Program P-Flash’ in the BDM
unsecuring description,
- Added requirement that user not write any Flash module register during
execution of commands ‘Erase All Blocks’,
Flash’,
- Added statement that security is released upon successful completion of
command ‘Erase All Blocks’,
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
Section 27.4.2.11
Section 27.5.2
Description of Changes
Section 27.4.2.8
Section
27.4.2.8, and ‘Unsecure
1017