S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 554

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
14.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Read: Anytime
Write: Anytime
554
Module Base + 0x0023
Module Base + 0x0024
Module Base + 0x0025
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
W
R
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
PACNT7
PACNT7
0
0
0
7
7
7
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
Figure 14-39. Pulse Accumulators Count Register 2 (PACN2)
Figure 14-40. Pulse Accumulators Count Register 1 (PACN1)
Figure 14-41. Pulse Accumulators Count Register 0 (PACN0)
PACNT6
PACNT6
0
0
0
6
6
6
MC9S12XE-Family Reference Manual Rev. 1.23
PACNT5
PACNT5
5
0
5
0
5
0
PACNT4
PACNT4
NOTE
0
0
0
4
4
4
PACNT3
PACNT3
0
0
0
3
3
3
PACNT2
PACNT2
2
0
2
0
2
0
PACNT1(9)
PACNT1
PACNT1
Freescale Semiconductor
0
0
0
1
1
1
PACNT0(8)
PACNT0
PACNT0
0
0
0
0
0
0