S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 860

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
24.3.2.12 EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
24.3.2.13 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
860
Offset Module Base + 0x000C
Offset Module Base + 0x000D
Reset
Reset
W
W
R
R
0
0
7
7
CCOBIX[2:0]
= Unimplemented or Reserved
= Unimplemented or Reserved
011
100
101
Table 24-26. FCCOB - NVM Command Mode (Typical Usage)
Figure 24-19. EEE Tag Counter Low Register (ETAGLO)
Figure 24-18. EEE Tag Counter High Register (ETAGHI)
0
0
6
6
Section
MC9S12XE-Family Reference Manual , Rev. 1.23
Byte
LO
LO
LO
HI
HI
HI
0
0
5
5
24.3.2.4). Once ECC fault information has been stored, no other
FCCOB Parameter Fields (NVM Command Mode)
0
0
4
4
ETAG[15:8]
ETAG[7:0]
Data 1 [15:8]
Data 2 [15:8]
Data 3 [15:8]
Data 1 [7:0]
Data 2 [7:0]
Data 3 [7:0]
0
0
3
3
0
0
2
2
Freescale Semiconductor
0
0
1
1
0
0
0
0