S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 182
S912XEP100J5MAGR
Manufacturer Part Number
S912XEP100J5MAGR
Description
S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEP100J5MAG.pdf
(1328 pages)
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Chapter 2 Port Integration Module (S12XEPIMV1)
This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports.
2.4
2.4.1
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output from the external bus interface module or a peripheral module or an input to the external bus
interface module or a peripheral module.
2.4.2
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and
ATD ports
not become active.
This device does not become active while the port is used as a push-pull output.
182
Functional Description
(Table
General
Registers
2-103). All registers can be written at any time, however a specific configuration might
Module
SCI3
CS3
CS2
CS1
CS0
IIC0
MC9S12XE-Family Reference Manual , Rev. 1.23
Example 2-1. Selecting a pull-up device
Table 2-102. Port F Routing Summary
5
0
1
x
x
x
x
x
x
x
x
x
x
4
x
x
0
1
x
x
x
x
x
x
x
x
PTFRR
3
x
x
x
x
0
1
x
x
x
x
x
x
2
x
x
x
x
x
x
0
1
x
x
x
x
1
0
1
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
0
1
TXD
PM7
SCL
PF7
PF5
PF3
PF2
PF1
PF0
PJ7
PJ0
PJ5
PJ2
PJ4
CS
Related Pins
RXD
PM6
SDA
PF6
PF4
PJ6
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