S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 262

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 5 External Bus Interface (S12XEBIV4)
state operation (stretching) of the external bus access is done in emulation modes when accessing internal
memory or emulation memory addresses.
In both modes observation of the internal operation is supported through the external bus (internal
visibility).
5.5.2.1
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 5-5
The timing diagram for this operation is shown in:
The associated timing numbers are given in:
Timing considerations:
262
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Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’
Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
LSTRB has the same timing as RW.
shows the PRU connection with the available external bus signals in an emulator application.
Example 2a: Emulation Single-Chip Mode
ADDR[22:20]/ACC[2:0]
Figure 5-5. Application in Emulation Single-Chip Mode
ADDR[22:0]/IVD[15:0]
S12X_EBI
MC9S12XE-Family Reference Manual , Rev. 1.23
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
ECLKX2
LSTRB
ECLK
RW
EMULMEM
PRU
Emulator
PRR
Ports
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