S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 491

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

11.4.1.3
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.
11.4.1.4
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
A time window of 50000 PLLCLK cycles
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See
1. IPLL is running at self clock mode frequency f
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Power on reset (POR)
Low voltage reset (LVR)
Wake-up from Full Stop Mode (exit full stop)
Clock Monitor fail indication (CM fail)
Clock Monitor (CM)
Clock Quality Checker
OSCCLK
PLLCLK
MC9S12XE-Family Reference Manual Rev. 1.23
1
1
Figure 11-17. Check Window Example
2
2
SCM
3
1
.
is called check window.
4
3
CHECK WINDOW
5
4095
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
OSC OK
4096
Figure 11-17
49999
as an example.
50000
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