S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 96

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 2 Port Integration Module (S12XEPIMV1)
96
Port
E
K
Pin Name
PK[6:4]
PK[3:0]
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
PE[1]
PE[0]
PK[7]
Pin Function
IQSTAT[3:0]
ADDR[22:20]
ADDR[19:16]
EROMCTL
& Priority
ROMCTL
ACC[2:0]
XCLKS
ECLKX2
MODB
MODA
TAGLO
LSTRB
EWAIT
TAGHI
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
XIRQ
GPIO
GPIO
GPIO
LDS
IRQ
mux
mux
GPI
GPI
RW
WE
RE
2
2
2
(1)
3
2
2
3
MC9S12XE-Family Reference Manual , Rev. 1.23
I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
O Read enable signal
O Free-running clock output at the Bus Clock rate or programmable
O Low strobe bar output
O Lower data strobe
O Read/write output for external bus
O Write enable signal
O Extended external bus address output
O Extended external bus address output
I
I
I
I
I
I
I
I
I
I
I
I
I
External clock selection input during RESET
Free-running clock output at Core Clock rate (ECLK x 2)
MODB input during RESET
Instruction tagging low pin
Configurable for reduced input threshold
MODA input during RESET
Instruction tagging low pin
Configurable for reduced input threshold
divided in normal modes
EROMON bit control input during RESET
Maskable level- or falling edge-sensitive interrupt input
General-purpose input
Non-maskable level-sensitive interrupt input
General-purpose input
ROMON bit control input during RESET
External Wait signal
Configurable for reduced input threshold
(multiplexed with access master output)
(multiplexed with instruction pipe status bits)
Description
Freescale Semiconductor
Pin Function
dependent
dependent
after Reset
Mode
Mode
4
3