S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 1095

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

28.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Freescale Semiconductor
ECCRIX[2:0]
Offset Module Base + 0x0004
Reset
IGNSF
Field
Field
CCIE
2-0
7
4
W
R
CCIE
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
being read. See
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
Flash Configuration Register (FCNFG)
0
7
generated
28.3.2.8).
= Unimplemented or Reserved
0
0
6
Section 28.3.2.13, “Flash ECC Error Results Register
Figure 28-9. Flash Configuration Register (FCNFG)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 28-14. FECCRIX Field Descriptions
Table 28-15. FCNFG Field Descriptions
0
0
5
IGNSF
0
4
Description
Description
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
0
0
3
(FECCR),” for more details.
0
0
2
FDFD
0
1
Section
28.3.2.7)
FSFD
0
0
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