S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 226

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S912XEP100J5MAGR

Manufacturer Part Number
S912XEP100J5MAGR
Description
S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
Manufacturer
Freescale Semiconductor
Datasheet

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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.5.3.2
In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set,
the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external
bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU
actions (see
3.5.3.3
In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set,
the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the
data (see
226
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Figure
Figure
ROM Control in Emulation Single-Chip Mode
ROM Control in Normal Expanded Mode
3-26).
3-25).
MCU
MCU
Figure 3-25. ROM in Emulation Single-Chip Mode
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 3-24. ROM in Single Chip Modes
Flash
MCU
Flash
No External Bus
Emulator
Emulator
EROMON = 1
EROMON = 0
Flash
Generator
Observer
Freescale Semiconductor

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