S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 88

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S912XEP100J5MAGR

Manufacturer Part Number
S912XEP100J5MAGR
Description
S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
Manufacturer
Freescale Semiconductor
Datasheet

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Chapter 1 Device Overview MC9S12XE-Family
1.13
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used. For this device XCLKS is mapped to PE7.
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.
88
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Power on reset or low-voltage reset
Clock monitor reset
Any reset while in self-clock mode or full stop mode
Oscillator Configuration
Figure 1-10. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
Figure 1-11. Full Swing Pierce Oscillator Connections (XCLKS = 0)
MCU
Figure 1-12. External Clock Connections (XCLKS = 0)
EXTAL
XTAL
MC9S12XE-Family Reference Manual , Rev. 1.23
MCU
MCU
EXTAL
EXTAL
XTAL
R
XTAL
B
=1MΩ ; R
R
S
R
B
S
Not Connected
specified by crystal vendor
Ceramic Resonator
Crystal or
CMOS-Compatible
External Oscillator
C
C
Ceramic Resonator
1
2
Crystal or
C
C
1
2
V
SSPLL
V
SSPLL
Freescale Semiconductor

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