S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 823

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

23.3.2.2
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
Freescale Semiconductor
0x02F1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reserved
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
HTEN
HTDS
VSEL
Field
HTIE
HTIF
VAE
7, 6
5
4
3
2
1
0
W
R
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
Voltage Access Select Bit — If set, the bandgap reference voltage V
multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
See device level specification for connectivity.
0 An internal temperature proportional voltage V
1 Bandgap reference voltage V
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
1 Voltage selected by VSEL can be accessed internally.
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
High Temperature Detect Status Bit —
This read-only status bit reflects the temperature status. Writes have no effect.
0 Temperature T
1 Temperature T
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no
effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
Control Register (VREGCTRL)
0
0
7
to Digital Converter channel).
= Unimplemented or Reserved
0
0
6
DIE
DIE
is below level T
is above level T
Figure 23-3. Control Register (VREGCTRL)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 23-3. VREGHTCL Field Descriptions
5
0
0
BG
can be accessed internally if VAE is set.
HTID
HTIA
or RPM or Shutdown Mode.
and FPM.
0
0
4
Description
HT
can be accessed internally if VAE is set.
0
0
3
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
BG
LVDS
can be accessed internally (i.e.
2
0
LVIE
0
1
LVIF
0
0
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