S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 1043
S912XEQ384J3MALR
Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ384J3MAL.pdf
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fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
All FECCR bits are readable but not writable.
Freescale Semiconductor
Offset Module Base + 0x000E
Offset Module Base + 0x000F
Reset
Reset
1. Double bit fault over single bit fault
2. CPU over XGATE
W
W
R
R
0
0
7
7
ECCRIX[2:0]
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 27-21. Flash ECC Error Results Low Register (FECCRLO)
Figure 27-20. Flash ECC Error Results High Register (FECCRHI)
000
001
010
011
100
101
110
111
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.24
Parity bits read from
Table 27-27. FECCR Index Settings
Flash block
Bits [15:8]
0
0
5
5
Not used, returns 0x0000 when read
Not used, returns 0x0000 when read
Data 1 [15:0] (P-Flash only)
Data 2 [15:0] (P-Flash only)
Data 3 [15:0] (P-Flash only)
FECCR Register Content
0
0
4
4
ECCR[15:8]
Global address [15:0]
ECCR[7:0]
CPU or XGATE
source identity
Data 0 [15:0]
Bit[7]
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
0
0
3
3
Global address
0
0
2
2
Bits[6:0]
[22:16]
0
0
1
1
0
0
0
0
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