S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 426

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
Chapter 10 XGATE (S12XGATEV3)
CPCH
Operation
RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated
Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of
the source register RD using binary subtraction and updates the condition code register accordingly. The
carry bit and Zero bits are taken into account to allow a 16 bit compare in the form of
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
Code and CPU Cycles
426
N:
Z:
V:
C:
CPCH RD, #IMM8
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $00 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15]
Z
CMPL
CPCH
BCC
V
Source Form
C
R2,#LOWBYTE
R2,#HIGHBYTE
Compare Immediate 8 bit Constant with
MC9S12XE-Family Reference Manual Rev. 1.24
Address
Mode
IMM8
; branch condition
Carry (High Byte)
1
1
0
1
1
Machine Code
RS
IMM8
CPCH
Freescale Semiconductor
Cycles
P

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