S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 435

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

LSL
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
LSL RD, #IMM4
LSL RD, RS
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Z
∆
old
V
∆
Source Form
^ RD[15]
C
∆
new
C
MC9S12XE-Family Reference Manual Rev. 1.24
Address
Mode
IMM4
DYA
Logical Shift Left
RD
0
0
n
0
0
0
0
0
0
1
1
Machine Code
RD
RD
0
0
n bits
RS
IMM4
0
Chapter 10 XGATE (S12XGATEV3)
0
1
1
0
1
1
0
0
LSL
0
0
Cycles
P
P
435