S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 594

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

DA
CL
DA
CL
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
Signal
15.4.1.1
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
594
Signal
Start
Start
SCL
SDA
MSB
MSB
ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
1
1
2
2
START Signal
Calling Address
START Condition
Calling Address
3
3
4
4
5
5
Figure 15-10. IIC-Bus Transmission Signals
MC9S12XE-Family Reference Manual Rev. 1.24
Figure 15-11. Start and Stop Conditions
6
6
7
7
Read/
Write
Read/
Write
LSB
LSB
8
8
Ack
Ack
Bit
9
Bit
9
XX
Repeated
XXX
Signal
Start
MSB
MSB
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
D7
1
1
D6
2
2
New Calling Address
D5
3
3
STOP Condition
Data Byte
D4
4
4
D3
5
5
Freescale Semiconductor
Figure
D2
6
6
D1
7
7
15-10, a
Read/
Write
LSB
LSB
D0
8
8
Ack
No
Bit
Ack
9
No
9
Bit