S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 267

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

6.3.2.1
Read: Anytime
Write: Anytime
6.3.2.2
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: 0x0121
Address: 0x0126
IVB_ADDR[7:0]
XILVL[2:0]
Reset
Reset
Field
2–0
Field
7–0
W
W
R
R
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
Interrupt Vector Base Register (IVBR)
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
1
0
0
7
7
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
Figure 6-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
accesses to this register will return all 0.
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
= Unimplemented or Reserved
1
0
0
6
6
Figure 6-3. Interrupt Vector Base Register (IVBR)
MC9S12XE-Family Reference Manual Rev. 1.24
Table 6-5. INT_XGPRIO Field Descriptions
Table 6-4. IVBR Field Descriptions
1
0
0
5
5
IVB_ADDR[7:0]
1
0
0
4
4
Description
Description
1
0
0
3
3
1
0
2
2
Chapter 6 Interrupt (S12XINTV2)
XILVL[2:0]
1
0
1
1
1
1
0
0
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