S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 453

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

SUB
Operation
RS1 – RS2
RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8])
Subtracts two 16 bit values and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
SUB RD, RS1, RS2
SUB RD, #IMM16
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Refer to SUBH instruction for #IMM16 operations.
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Refer to SUBH instruction for #IMM16 operations.
Z
∆
V
∆
Source Form
⇒ RD
When using immediate addressing mode (SUB RD, #IMM16), the V-flag
and the C-Flag of the first instruction (SUBL RD, #IMM16[7:0]) are not
considered by the second instruction (SUBH RD, #IMM16[15:8]).
⇒ Don’t rely on the V-Flag if RD - IMM16[7:0] < −2
⇒ Don’t rely on the C-Flag if RD < IMM16[7:0].
C
∆
new
MC9S12XE-Family Reference Manual Rev. 1.24
| RS1[15] & RS2[15] & RD[15]
Address
Mode
IMM8
IMM8
new
TRI
Subtract without Carry
| RS2[15] & RD[15]
0
1
1
NOTE
0
1
1
0
0
0
1
0
0
new
new
1
0
1
Machine Code
RD
RD
RD
15
.
RS1
IMM16[15:8]
IMM16[7:0]
Chapter 10 XGATE (S12XGATEV3)
RS2
SUB
0
0
Cycles
P
P
P
453