S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 544

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
544
PR[2:0]
TCRE
Field
TOI
2:0
7
3
TC7 event
TC7
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock".
Note: in
Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
When TCRE is set and TC7 is not equal to 0, TCNT will cycle from 0 to TC7. When TCNT reaches TC7
value, it will last only one bus cycle then reset to 0. for a more detail explanation please refer to
17.
Figure
prescaler
counter
Figure 14-17. The TCNT cycle diagram under TCRE=1 condition
0
14-17,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock
PR2
0
0
0
0
1
1
1
1
MC9S12XE-Family Reference Manual Rev. 1.24
Table 14-15. TSCR2 Field Descriptions
Table 14-16. Prescaler Selection
1
PR1
0
0
1
1
0
0
1
1
PR0
-----
0
1
0
1
0
1
0
1
Description
Table
Prescale Factor
TC7-1
14-16.
128
16
32
64
1
2
4
8
TC7 event
1 bus
clock
TC7
Freescale Semiconductor
0
Figure 14-