S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 204

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 3 Memory Mapping Control (S12XMMCV4)

The reset value of 0xFE ensures that there is a linear EEPROM space available between addresses 0x0800

and 0x0FFF out of reset.

The ﬁxed 1K page 0x0C00–0x0FFF of EEPROM is equivalent to page 255 (page number 0xFF).

The MMC block performs several basic functions of the S12X sub-system operation: MCU operation

modes, priority control, address mapping, select signal generation and access limitations for the system.

Each aspect is described in the following subsections.

Normal single-chip mode

There is no external bus in this mode. The MCU program is executed from the internal memory

and no external accesses are allowed.

Special single-chip mode

This mode is generally used for debugging single-chip operation, boot-strapping or security related

operations. The active background debug mode is in control of the CPU code execution and the

BDM ﬁrmware is waiting for serial commands sent through the BKGD pin. There is no external

bus in this mode.

Functional Description

MCU Operating Mode

EEPROM Page Index Bits 7–0 — These page index bits are used to select which of the 256 EEPROM array

pages is to be accessed in the EEPROM Page Window.

MC9S12XE-Family Reference Manual Rev. 1.24

Figure 3-16. EPAGE Address Mapping

Table 3-15. EPAGE Field Descriptions

Global Address [22:0]

EPAGE Register [7:0]

Address: CPU Local Address

or BDM Local Address

Address [9:0]

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