S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 705

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

Read: Anytime
Write: Anytime (causes the scale counter to load the PWMSCLB value).
19.3.2.11 Reserved Registers (PWMSCNTx)
The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are
not available in normal modes.
Read: Always read $00 in normal modes
Write: Unimplemented in normal modes
19.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 19.4.2.5, “Left Aligned Outputs”
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, see
“PWM Timer
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Freescale Semiconductor
Module Base + 0x000A, 0x000B
Reset
W
R
0
0
7
Counters”.
Writing to these registers when in special modes can alter the PWM
functionality.
= Unimplemented or Reserved
0
0
6
Figure 19-13. Reserved Registers (PWMSCNTx)
MC9S12XE-Family Reference Manual Rev. 1.24
0
0
5
and
Section 19.4.2.6, “Center Aligned Outputs”
NOTE
0
0
4
0
0
3
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
0
0
2
0
0
1
Section 19.4.2.4,
for more
0
0
0
705